The present inventive concept relates to semiconductor memories. More particularly, the inventive concept relates to a method of controlling a deep power down mode in a multi-port semiconductor memory.
Semiconductor devices, such as a dynamic random access memory (DRAM) and the like, are often used as the main memory element in various electronic systems. Within many contemporary applications, semiconductor memories are required to operate at high speed. Additionally, a very high degree of integration density is demanded for semiconductor memories.
In recent years, semiconductor memories have been increasingly used in mobile electronic devices, such as a mobile phones or the like. In this capacity, multi-port semiconductor memories allow a plurality of computational or logic components (generically hereafter “processors”) to access internal memory banks via through different data input/output (I/O) ports. Additionally, the conservation of power, especially battery power, is critical to the commercial success of mobile electronic devices. Accordingly, these devices are configured to operate in a so-called “deep power down mode” of operation in which a minimum of power is consumed. Thus, in multi-port semiconductor memories, the efficient control (i.e., entering and exiting) of a deep power down mode is important in operating aspect.
In conventional semiconductor memories, a “standby mode” of operation is provided in which power consumption is greatly reduced, as compared with an active mode of operation. However, if a semiconductor memory remains in the standby mode for a defined period of time, it may enter the deep power down mode of operation in which power consumption is further reduced. For example, certain peripheral circuits may be fully disabled upon entering the deep power down mode.
The activation (i.e., entering) and deactivation (exiting) of a deep power down mode is further complicated when a multi-port semiconductor memory is used in a particular host device. That is, since a plurality of processors may access data from the internal memory banks via different ports under different conditions in a mobile host device, the definition, timing, and inter-processor coordination of deep power down mode activation/deactivation must be carefully considered.